(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method to eliminate a layout-dependent problem of cracks occurring in layers of Inter Metal Dielectric (IMD) oxide.
(2) Description of the Prior Art
The creation of semiconductor devices requires the creation of multiple device elements that must are interconnected in order to form a functional device. Where device elements are required to be electrically isolated from each other, this isolation is accomplished by providing separating layers of semiconductor material between these elements. These separating layers not only perform the function of electrically isolating active elements of semiconductor devices from each other but additionally provide sealing the devices from outside influences and conditions while the separating layers are typically used to provide support for overlying layers of patterned semiconductor material. Conventionally, an upper layer of passivation material is deposited over the surface of a completed device, providing protection for the multiple underlying devices against environmental effects such as moisture or impurities in addition to providing protection during further processing of the device such as packaging the device.
The application of layers of Inter Metal Dielectric (IMD) and Intra Level Dielectric (ILD) is well known in the art. In the field of high density interconnect technology, many integrated circuit chips are physically and electrically connected to a single substrate. To achieve a high wiring and packing density, it is necessary to fabricate a multilayer structure on the substrate to connect integrated circuits to one another. Typically, metal power and ground planes in the substrate are separated by layers of a dielectric. Embedded in other dielectric layers are metal conductor lines with vias holes providing electrical connections between signal lines or to the metal power and ground planes. To avoid problems of depth of focus and the like during the process of photolithography that is part of the creation of interconnect patterns, it is important to produce patterned layers that are substantially flat and smooth (i.e., planar) to serve as the base for the next layer. A non-flat surface results in photoresist thickness variations that require pattern or layer dependent processing conditions, greatly increasing the problem complexity and leading to line width variation and reduced yield.
Improved device performance is typically and by necessity obtained by continued reduction in device dimensions. It is therefore not uncommon to have devices, of for instance logic devices, that have device feature dimensions of sub-micron and deep sub-micron values, such as 0.25 xcexcm and even down to 0.18 xcexcm. For devices of such small dimensions, the creation of surrounding layers of dielectric presents a special challenge. The layer of dielectric correspondingly will be created having smaller dimensions since proximity of device features cannot be sacrificed due to the decrease in device feature dimensions. Device densities increase therefore with increasing device miniaturization. This results in creating patterns of strain in layers of dielectric, which have been known to cause fissures or cracks in the created layers of dielectric. These cracks will most naturally occur where the stress in the created layer of dielectric is highest, which is in corners or abrupt changes in the cross section of the created layer of dielectric.
The invention specifically addresses the occurrence of cracks in layers of IMD oxide where these layers are created as part of devices having deep-submicron dimensions. It has been found that IMD oxide defect is essentially layout-dependent and that this defect is therefore present at known locations within the deposited layer of IMD oxide. Creating layers of IMD oxide of higher deposition densities can reduce IMD oxide crack. Lacking thereby however is an effective quantitative method that can be applied to gain additional insight in predicting when and under which conditions of IMD oxide deposition flaws in the deposited layer of IMD oxide, such as cracks, are most likely to occur. The invention addresses this issue.
U.S. Pat. No. 6,093,620 (Peltzer) reveals an oxide crack problem.
U.S. Pat. No. 5,788,767 (Ko et al.) discloses a pinhole test for oxide cracks.
U.S. Pat. No. 6,046,102 (Bothra et al.) and U.S. Pat. No. 5,266,525 (Morozumi) are related patents showing aspects of IMD""S.
A principle objective of the invention is to remove the occurrence of irregularities such as cracks in a layer of IMD oxide that is created as part of the process of creating semiconductor devices having deep sub-micron device features.
Another objective of the invention is to provide a pattern in a layer of IMD oxide that monitors the occurrence of IMD oxide cracking.
Yet another objective of the invention is to provide design rules used for the creation of semiconductor devices that are aimed at preventing the occurrence of IMD oxide cracking.
In accordance with the objectives of the invention a new method is provided to monitor and to prevent IMD oxide irregularities such as IMD oxide cracks. A monitoring pattern is inserted in the test line of the fabrication substrate to monitor the strength of the created layer of IMD oxide. Variations in the characteristics of the created layer of IMD oxide can in this manner be detected. In addition, design rules are provided that are aimed at avoiding layers of IMD oxide that have proven or are known to be particularly prone to the occurrence of IMD oxide cracks.